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ProgramsBCASemester 1Digital LogicUnit 3: Combinational Logic Design
Chapter Study

BCA Semester 1 – Digital Logic – Unit 3: Combinational Logic Design

Comprehensive questions and detailed answers for Unit 3: Combinational Logic Design. Perfect for exam preparation and concept clarity.

20
Questions
120
Marks
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1

Simplify (using k-map) the given Boolean function in both SOP and POS using the don't care condition if:

f(A,B,C,D)=ℼ(0,1,3,7,8,12)ℼd(5,10,13,14)f(A, B, C, D) = ℼ(0,1,3,7,8,12) ℼ d(5,10,13,14)f(A,B,C,D)=ℼ(0,1,3,7,8,12)ℼd(5,10,13,14).

MediumTHEORY5 marks2019(TU FOHSS Final)
2

Define decoder. Draw logic diagram and truth table of 3 to 8 line decoder.

MediumTHEORY5 marks2019(TU FOHSS Final)
3

Define ROM. Implement the following combinational logic function using ROM: image

MediumTHEORY5 marks2019(TU FOHSS Final)
4

Define PLA. Design PLA circuit with given function. F1(A,B,C)=Σ(3,5,6,7)F1(A, B, C) = Σ(3,5,6,7)F1(A,B,C)=Σ(3,5,6,7)

F2(A,B,C)=Σ(0,2,4,7)F2(A, B, C) = Σ(0,2,4,7)F2(A,B,C)=Σ(0,2,4,7)

Design PLA Program table also.

HardTHEORY10 marks2019(TU FOHSS Final)
5

Define universal gate. Explain Universal gates with their graphical symbol, algebraic expression, truth table, and Venn diagram.

MediumTHEORY5 marks2020(TU FOHSS Final)
6

Define Decoder. Explain binary to octal converter with block diagram, truth table and logic diagram.

MediumTHEORY5 marks2020(TU FOHSS Final)
7

Simplify the Boolean function F(w, x, y, z) = π(0,2,4,6,8,10,12,14) and don’t care conditions d(w, x, y, z) = π(1,3,9,11) using K-Map method for both SOP and POS form.

MediumTHEORY5 marks2020(TU FOHSS Final)
8

Define Multiplexer. Explain 4:1 multiplexer with its block diagram, truth table and logic diagram.

MediumTHEORY5 marks2020(TU FOHSS Final)
9

Simplify given Boolean function in both SOP and POS using k-map where d represents don't care condition.F (A, B, C, D) = ∏ (2, 3, 4, 5, 7, 9, 10) and ∏ d (0, 6, 11)

MediumTHEORY5 marks2021(TU FOHSS Final)
10

Define combinational logic circuit. Design a full adder with its truth table, logic diagram and Boolean expression.

MediumTHEORY5 marks2021(TU FOHSS Final)
11

Define Decoder. Design BCD to Decimal decoder with its block diagram, truth table, circuit diagram and mathematical expression.

MediumTHEORY5 marks2021(TU FOHSS Final)
12

Explain basic gates and universal gate. Realize NOR gate as a universal gate.

MediumTHEORY5 marks2021(TU FOHSS Final)
13

Explain PLA with its block diagram. Design a combinational circuit using a ROM that accepts a 3-bit number and generates an output binary number equal to the square of the input number with circuit diagram, truth table and block diagram.

HardTHEORY10 marks2021(TU FOHSS Final)
14

Define multiplexer. Explain 4:1 multiplexer with its block diagram, truth table and logic diagram. Mention how a 4:1 multiplexer works like lower order multiplexer.

HardTHEORY10 marks2021(TU FOHSS Final)
15

Simplify given Boolean function in both SOP and POS using k-map where d represents don't care condition.F (A, B, C, D) = ∏(0, 1, 3, 7, 8, 12) and ∏ d(5, 10, 13, 14)

MediumTHEORY5 marks2022(TU FOHSS Final)
16

Define combinational circuit. Write a combinational circuit design procedure. Design a half adder with its truth table, logic diagram and Boolean expression.

MediumTHEORY5 marks2022(TU FOHSS Final)
17

Define Priority encoder. Design 4:2 priority encoder with its block diagram, truth table, circuit diagram and mathematical expression.

MediumTHEORY5 marks2022(TU FOHSS Final)
18

Why NAND and NOR gates are called universal gates? Realize NAND gate as universal gate.

MediumTHEORY5 marks2022(TU FOHSS Final)
19

Define PLA with its block diagram. Realize BCD to gray code converter using PAL.

HardTHEORY10 marks2022(TU FOHSS Final)
20

Explain the universal gates with their logic symbol, logic expression, and truth table. Realize an OR Gate using NAND Gate.

MediumTHEORY5 marks2023(TU FOHSS Final)
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2024
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2023
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TU FOHSS Final•5 questions
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2020
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2019
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Questions in Unit 3: Combinational Logic Design

Simplify (using k-map) the given Boolean function in both SOP and POS using the don't care condition if: \(f(A, B, C, D) = ℼ(0,1,3,7,8,12) ℼ d(5,10,13,14)\).

Marks: 5

Year: 2019 Final TU FOHSS

Given: \( f(A,B,C,D) = \Pi(0,1,3,7,8,12) \) with don’t-care \( d(5,10,13,14) \) --- Key idea – how to handle don’t-care in K-map - Don’t-care cells (d) can be treated as either 1 or 0 — whiche

Define decoder. Draw logic diagram and truth table of 3 to 8 line decoder.

Marks: 5

Year: 2019 Final TU FOHSS

Definition of Decoder A decoder is a combinational logic circuit that takes an n-bit binary input and produces up to 2ⁿ output lines, such that for each input combination exactly one output is activ

Define ROM. Implement the following combinational logic function using ROM:

Marks: 5

Year: 2019 Final TU FOHSS

Definition: Read‑Only Memory (ROM) - ROM is a non‑volatile memory that stores fixed binary data (0s and 1s) which cannot be (easily) changed during normal operation. - Internally, a ROM has k add

Define PLA. Design PLA circuit with given function. \(F1(A, B, C) = Σ(3,5,6,7)\) \(F2(A, B, C) = Σ(0,2,4,7)\) Design PLA Program table also.

Marks: 10

Year: 2019 Final TU FOHSS

1. Definition of PLA PLA (Programmable Logic Array) is a combinational logic device used to implement multiple Boolean functions. - It consists of two levels of logic: 1. Programmable AND plane

Define universal gate. Explain Universal gates with their graphical symbol, algebraic expression, truth table, and Venn diagram.

Marks: 5

Year: 2020 Final TU FOHSS

1. Definition of Universal Gate A universal gate is a logic gate that can be used to implement any Boolean function (AND, OR, NOT, etc.) without using any other gate. - NAND and NOR are universal ga

Define Decoder. Explain binary to octal converter with block diagram, truth table and logic diagram.

Marks: 5

Year: 2020 Final TU FOHSS

1. Definition of Decoder A decoder is a combinational circuit that converts n input lines into 2ⁿ unique output lines. - Each output corresponds to one combination of input values. - Used in memor

Simplify the Boolean function F(w, x, y, z) = π(0,2,4,6,8,10,12,14) and don’t care conditions d(w, x, y, z) = π(1,3,9,11) using K-Map method for both SOP and POS form.

Marks: 5

Year: 2020 Final TU FOHSS

1. Given Function \[ F(w, x, y, z) = \prod M(0,2,4,6,8,10,12,14) \] Don't care conditions: \[ d(w, x, y, z) = \prod M(1,3,9,11) \] > Note: π represents product of maxterms (POS form). --- 2. St

Define Multiplexer. Explain 4:1 multiplexer with its block diagram, truth table and logic diagram.

Marks: 5

Year: 2020 Final TU FOHSS

1. Definition of Multiplexer A Multiplexer (MUX) is a combinational circuit that selects one of many inputs and sends it to a single output line based on select lines. - Also called a data selector.

Simplify given Boolean function in both SOP and POS using k-map where d represents don't care condition.F (A, B, C, D) = ∏ (2, 3, 4, 5, 7, 9, 10) and ∏ d (0, 6, 11)

Marks: 5

Year: 2021 Final TU FOHSS

1. Given Function \[ F(A, B, C, D) = \prod M(2, 3, 4, 5, 7, 9, 10) \] Don't care conditions: \[ d(A, B, C, D) = \prod M(0, 6, 11) \] > π denotes product of maxterms (POS form). --- 2. Step 1: C

Define combinational logic circuit. Design a full adder with its truth table, logic diagram and Boolean expression.

Marks: 5

Year: 2021 Final TU FOHSS

1. Definition: Combinational Logic Circuit - A Combinational Logic Circuit is a type of digital circuit where output depends only on the current input values, not on past inputs (no memory). - Chara

Define Decoder. Design BCD to Decimal decoder with its block diagram, truth table, circuit diagram and mathematical expression.

Marks: 5

Year: 2021 Final TU FOHSS

1. Definition of Decoder - A Decoder is a combinational circuit that converts n input lines into a maximum of 2ⁿ unique outputs, with only one output active at a time. - Purpose: To decode a binary

Explain basic gates and universal gate. Realize NOR gate as a universal gate.

Marks: 5

Year: 2021 Final TU FOHSS

1. Basic Logic Gates | Gate | Symbol | Function | Boolean Expression | Truth Table | |------|--------|---------|-----------------|-------------| | AND | A⋅B | Output is 1 if both inputs are 1 | F = A⋅

Explain PLA with its block diagram. Design a combinational circuit using a ROM that accepts a 3-bit number and generates an output binary number equal to the square of the input number with circuit di

Marks: 10

Year: 2021 Final TU FOHSS

1. Programmable Logic Array (PLA) - Definition: A PLA is a programmable device used to implement combinational logic circuits. It consists of a programmable AND plane and a programmable OR plane.

Define multiplexer. Explain 4:1 multiplexer with its block diagram, truth table and logic diagram. Mention how a 4:1 multiplexer works like lower order multiplexer.

Marks: 10

Year: 2021 Final TU FOHSS

1. Definition - A Multiplexer (MUX) is a combinational circuit that selects one input from many inputs and sends it to a single output line based on select lines. - Function: Data selector. - Appl

Simplify given Boolean function in both SOP and POS using k-map where d represents don't care condition.F (A, B, C, D) = ∏(0, 1, 3, 7, 8, 12) and ∏ d(5, 10, 13, 14)

Marks: 5

Year: 2022 Final TU FOHSS

Given Function - F(A, B, C, D) = Π(0, 1, 3, 7, 8, 12) - Don't care conditions: d(A, B, C, D) = Π(5, 10, 13, 14) We are to find SOP and POS forms. --- Step 1: Construct K-Map (4-variable) | AB\CD

Define combinational circuit. Write a combinational circuit design procedure. Design a half adder with its truth table, logic diagram and Boolean expression.

Marks: 5

Year: 2022 Final TU FOHSS

1. Definition of Combinational Circuit - A combinational circuit is a logic circuit whose output depends only on the current inputs. - No memory elements or feedback are used. - Examples: Adders,

Define Priority encoder. Design 4:2 priority encoder with its block diagram, truth table, circuit diagram and mathematical expression.

Marks: 5

Year: 2022 Final TU FOHSS

4:2 Priority Encoder — Corrected Answer Definition A priority encoder encodes the index of the highest-priority active input among many inputs. For a 4:2 priority encoder inputs are I3 (highest), I2,

Why NAND and NOR gates are called universal gates? Realize NAND gate as universal gate.

Marks: 5

Year: 2022 Final TU FOHSS

Definition A universal gate is a logic gate that can be used to implement any Boolean function using only that type of gate. Reason NAND and NOR gates are called universal gates because: - Any basic

Define PLA with its block diagram. Realize BCD to gray code converter using PAL.

Marks: 10

Year: 2022 Final TU FOHSS

1. Definition: PLA - PLA (Programmable Logic Array) is a combinational logic device used to implement multiple Boolean functions. - Features: - Programmable AND plane (for product terms / minterms)

Explain the universal gates with their logic symbol, logic expression, and truth table. Realize an OR Gate using NAND Gate.

Marks: 5

Year: 2023 Final TU FOHSS

1. Universal Gates Universal gates can be used to implement any Boolean function (AND, OR, NOT, etc.). a) NAND Gate Logic Expression: \[ F = \overline{A \cdot B} \] Truth Table: | A | B | F = A NAN

About Unit 3: Combinational Logic Design Questions

This page contains comprehensive questions from the Unit 3: Combinational Logic Design chapter of Digital Logic, part of the BCA Semester 1 curriculum. All questions include detailed model answers from past TU exam papers.

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Unit 3: Combinational Logic Design chapter questions with answers for Digital Logic (BCA Semester 1). Prepare for TU exams with our comprehensive question bank and model answers.

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