What are the drawbacks of clocked RS Flip Flop? Explain the operation of JK Flipflop along with its circuit diagram and characteristic table.
Marks: 5
Year: 2019 Final TU FOHSS
Drawbacks of Clocked RS Flip‑Flop - The basic (clocked) RS Flip‑Flop (or gated RS) has a fundamental problem when both inputs S (Set) and R (Reset) are 1 — this creates an invalid / undefined state