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ProgramsBCASemester 2Microprocessor and Comp. ArchitectureUnit 1: Fundamental of Microprocessor (5Hrs)
Chapter Study

BCA Semester 2 – Microprocessor and Comp. Architecture – Unit 1: Fundamental of Microprocessor (5Hrs)

Comprehensive questions and detailed answers for Unit 1: Fundamental of Microprocessor (5Hrs). Perfect for exam preparation and concept clarity.

11
Questions
70
Marks
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1

Explain the bus organization of 8085 microprocessor.

MediumTHEORY5 marks2019(TU FOHSS Final)
2

Explain the functional block of 8085 microprocessor.

HardTHEORY10 marks2019(TU FOHSS Final)
3

Define instruction cycle. Explain the opcode fetch machine cycle for MOV A, B with timing diagram. (Opcode: MOV A, B = 78h)

MediumTHEORY5 marks2020(TU FOHSS Final)
4

Define instruction set. Classify the instructions available in 8085 with example.

HardTHEORY10 marks2020(TU FOHSS Final)
5

Define the addressing mode. Explain the various instruction addressing modes with example.

HardTHEORY10 marks2020(TU FOHSS Final)
6

Explain the addressing modes of 8085 with suitable example.

MediumTHEORY5 marks2021(TU FOHSS Final)
7

Draw the timing diagram for MVI A, 35H and explain in brief.

MediumTHEORY5 marks2021(TU FOHSS Final)
8

What are the typical characteristics of CISC instruction set architecture? Explain.

MediumTHEORY5 marks2021(TU FOHSS Final)
9

What is the use of flag? Explain different flags of 8085 with an example.

MediumTHEORY5 marks2022(TU FOHSS Final)
10

Draw the timing diagram of LXI H, 5070H instruction.

MediumTHEORY5 marks2022(TU FOHSS Final)
11

Compare 8085 and 8086 microprocessors. Let A=454 and B=674, find the content of flag register when SUB B is performed.

MediumTHEORY5 marks2024(TU FOHSS Final)
Showing 11 questions

Exam Years

Past question papers

2024
TU FOHSS Final•1 questions
2022
TU FOHSS Final•2 questions
2021
TU FOHSS Final•3 questions
2020
TU FOHSS Final•3 questions
2019
TU FOHSS Final•2 questions

Questions in Unit 1: Fundamental of Microprocessor (5Hrs)

Explain the bus organization of 8085 microprocessor.

Marks: 5

Year: 2019 Final TU FOHSS

Bus Organization of 8085 The 8085 microprocessor uses three main buses to communicate with memory and I/O devices: 1. Address Bus - Unidirectional (only from CPU → memory). - 16-bit wide → c

Explain the functional block of 8085 microprocessor.

Marks: 10

Year: 2019 Final TU FOHSS

Introduction The 8085 microprocessor is an 8-bit microprocessor with a 40-pin IC. Its internal architecture contains several functional blocks that work together to execute instructions, perform ari

Define instruction cycle. Explain the opcode fetch machine cycle for MOV A, B with timing diagram. (Opcode: MOV A, B = 78h)

Marks: 5

Year: 2020 Final TU FOHSS

1. Definition of Instruction Cycle An instruction cycle is the complete process by which a microprocessor fetches, decodes, and executes an instruction. It consists of three main steps: 1. Fetch – R

Define instruction set. Classify the instructions available in 8085 with example.

Marks: 10

Year: 2020 Final TU FOHSS

1. Definition of Instruction Set An instruction set is the collection of all instructions that a microprocessor can execute. Each instruction tells the CPU to perform a specific operation like data

Define the addressing mode. Explain the various instruction addressing modes with example.

Marks: 10

Year: 2020 Final TU FOHSS

Define Addressing Mode Addressing Mode defines the method by which the operand of an instruction is specified. It tells the CPU where to find the data to be used in an operation — whether in a regis

Explain the addressing modes of 8085 with suitable example.

Marks: 5

Year: 2021 Final TU FOHSS

Addressing Modes of 8085 Definition: An addressing mode defines the method by which an operand of an instruction is specified. It tells the CPU where to find the data to perform an operation: in a

Draw the timing diagram for MVI A, 35H and explain in brief.

Marks: 5

Year: 2021 Final TU FOHSS

Timing Diagram for MVI A, 35H Instruction: MVI A, 35H Opcode: 3EH Purpose: Load immediate data 35H into accumulator A. --- Steps of Execution 1. Opcode Fetch (1st Machine Cycle) - T1: Place

What are the typical characteristics of CISC instruction set architecture? Explain.

Marks: 5

Year: 2021 Final TU FOHSS

Characteristics of CISC Instruction Set Architecture CISC (Complex Instruction Set Computer) is a CPU design philosophy where the instruction set contains a large number of complex instructions. Each

What is the use of flag? Explain different flags of 8085 with an example.

Marks: 5

Year: 2022 Final TU FOHSS

1. Definition of Flag Flag: A flag is a single-bit indicator used to show the status of an operation in the CPU. Uses of Flags: - Indicate results of arithmetic or logical operations (e.g., zero, ca

Draw the timing diagram of LXI H, 5070H instruction.

Marks: 5

Year: 2022 Final TU FOHSS

Instruction: LXI H, 5070H Purpose: Load the 16-bit immediate data (5070H) into H-L register pair. Opcode: 21H Instruction Size: 3 Bytes (Opcode + Low Byte + High Byte) --- Execution Steps 1. O

Compare 8085 and 8086 microprocessors. Let A=454 and B=674, find the content of flag register when SUB B is performed.

Marks: 5

Year: 2024 Final TU FOHSS

Comparison between 8085 and 8086 Microprocessors | Feature | 8085 | 8086 | |-------|---------|---------| | Word Size | 8-bit | 16-bit | | Data Bus | 8-bit | 16-bit | | Address Bus | 16-bit | 20-bit |

About Unit 1: Fundamental of Microprocessor (5Hrs) Questions

This page contains comprehensive questions from the Unit 1: Fundamental of Microprocessor (5Hrs) chapter of Microprocessor and Comp. Architecture, part of the BCA Semester 2 curriculum. All questions include detailed model answers from past TU exam papers.

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Unit 1: Fundamental of Microprocessor (5Hrs) chapter questions with answers for Microprocessor and Comp. Architecture (BCA Semester 2). Prepare for TU exams with our comprehensive question bank and model answers.

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